summaryrefslogtreecommitdiff
path: root/src/cpu/intel/model_6fx
diff options
context:
space:
mode:
authorLee Leahy <leroy.p.leahy@intel.com>2017-03-15 18:26:18 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-16 04:14:27 +0100
commitcdc50480c414df3b5f438f7f26a73df597e544ae (patch)
tree2b373cab7ce4679a534420579ae2790302166ce2 /src/cpu/intel/model_6fx
parent26eeb0f8ad554b1fa08d58080da8ce2d22081c1c (diff)
cpu/intel: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18850 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/model_6fx')
-rw-r--r--src/cpu/intel/model_6fx/model_6fx_init.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 4c13f12cb1..2a04a4e122 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -48,12 +48,14 @@ static void configure_c_states(void)
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;
- msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
+ msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff)
+ << 16);
wrmsr(MSR_PMG_IO_BASE_ADDR, msr);
/* Set C_LVL controls and IO Capture Address */
msr.hi = 0;
- msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
+ // -2 because LVL0+1 aren't counted
+ msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16);
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}