diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-25 21:38:25 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:45:34 +0000 |
| commit | 6336d4c48d2f85629ff668da36711ea794f70ab5 (patch) | |
| tree | 1cafe0dde00967c76897312d80fca723bf0a2f79 /src/cpu/intel/model_6fx | |
| parent | ea415b335f57bde8e744e0f40845cc6fdd671c71 (diff) | |
nb/intel/gm45: Use parallel MP init
This places the parallel mp ops up in the model_1067x dir and is
included from other Intel core2 CPU dirs that can use the same code.
Tested on Thinkpad X200 on which boot time is reduced by ~35ms.
Change-Id: Iac416f671407246ee223075eee1aff511e612889
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/23434
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_6fx')
| -rw-r--r-- | src/cpu/intel/model_6fx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/model_6fx_init.c | 12 |
2 files changed, 9 insertions, 4 deletions
diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index a0824fdb18..9564bf950e 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += model_6fx_init.c subdirs-y += ../../x86/name subdirs-y += ../common +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6fx/microcode.bin diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 9d11478dee..a502826c77 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -133,15 +133,18 @@ static void model_6fx_init(struct device *cpu) x86_enable_cache(); /* Update the microcode */ - intel_update_microcode_from_cbfs(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_update_microcode_from_cbfs(); /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { + x86_setup_mtrrs(); + x86_mtrr_check(); + } /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT @@ -162,7 +165,8 @@ static void model_6fx_init(struct device *cpu) configure_pic_thermal_sensors(); /* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); } static struct device_operations cpu_dev_ops = { |