diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
| commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
| tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/cpu/intel/model_6fx | |
| parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6fx')
| -rw-r--r-- | src/cpu/intel/model_6fx/Config.lb | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 14 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram_disable.c | 6 |
3 files changed, 12 insertions, 12 deletions
diff --git a/src/cpu/intel/model_6fx/Config.lb b/src/cpu/intel/model_6fx/Config.lb index 74f8be6168..7cbd118b99 100644 --- a/src/cpu/intel/model_6fx/Config.lb +++ b/src/cpu/intel/model_6fx/Config.lb @@ -1,5 +1,5 @@ -uses HAVE_MOVNTI -default HAVE_MOVNTI=1 +uses CONFIG_HAVE_MOVNTI +default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index d04274046d..5ce01cbd04 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> @@ -29,7 +29,7 @@ movl %eax, %ebp cache_as_ram: -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 post_code(0x20) @@ -108,18 +108,18 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 -#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ /* enable cache */ movl %cr0, %eax diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c index 981aac1399..ce508676e5 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c +++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c @@ -27,7 +27,7 @@ void stage1_main(unsigned long bist) { unsigned int cpu_reset = 0; -#if USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 /* Is this a deliberate reset by the bios */ if (bios_reset_detected() && last_boot_normal()) { goto normal_image; @@ -87,10 +87,10 @@ cpu_reset_x: } __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ + /* set new esp */ /* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE ) ); { |