diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-20 13:29:59 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 05:40:13 +0200 |
| commit | 8a2f167e7b99c171161937f52ccf5bc4ac9d6685 (patch) | |
| tree | d45b1c4f1060774fb7c4ed2b28f7ba6c1b3deae8 /src/cpu/intel/model_6ex | |
| parent | eb61ea84f7226d6c081441bbb6fbafbb920505db (diff) | |
intel car: Unify postcodes
Not all are matched, but this makes it easier to backport
MTRR changes from haswell.
Change-Id: Ida5943b1469fc0089a31ff3b18131fb82b0941c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_6ex')
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 9ae217c9e9..1f2445a2ab 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -47,24 +47,29 @@ clear_mtrrs: dec %edi jnz clear_mtrrs + post_code(0x22) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr + post_code(0x23) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr + post_code(0x24) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr + post_code(0x25) + /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -91,6 +96,7 @@ clear_mtrrs: xorl %eax, %eax rep stosl + post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -113,6 +119,7 @@ clear_mtrrs: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr + post_code(0x28) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -127,8 +134,8 @@ clear_mtrrs: movl %esp, %ebp pushl %eax - post_code(0x23) - +before_romstage: + post_code(0x29) /* Call romstage.c main function. */ call romstage_main @@ -137,8 +144,6 @@ clear_mtrrs: */ movl %eax, %ebx - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -154,7 +159,7 @@ clear_mtrrs: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x31) + post_code(0x32) invd |