summaryrefslogtreecommitdiff
path: root/src/cpu/intel/model_6ex
diff options
context:
space:
mode:
authorPatrick Georgi <patrick.georgi@secunet.com>2011-08-09 08:52:14 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2011-09-09 11:40:30 +0200
commitac624a638d25645f9a9a25ee2e16224aaf921b98 (patch)
tree0ebf9c2c9b287f74c10ffce7cf3a9cddd6361c33 /src/cpu/intel/model_6ex
parent7981b940a6bd703ae97f6c765c107ea7b4913dec (diff)
Crank up CPU speed on Intel Core and Core2 CPUs
The CPUs start on their slowest speed, and were left that way by coreboot. This change will speed up coreboot a bit, as well as systems that don't change the clock for whatever reason. Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/176 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_6ex')
-rw-r--r--src/cpu/intel/model_6ex/model_6ex_init.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index eee651a207..abd9cf4bc2 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -30,6 +30,7 @@
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/speedstep.h>
+#include <cpu/intel/acpi.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <usbdebug.h>
@@ -129,6 +130,19 @@ static void configure_misc(void)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
+
+ // set maximum CPU speed
+ msr = rdmsr(IA32_PERF_STS);
+ int busratio_max=(msr.hi >> (40-32)) & 0x1f;
+
+ msr = rdmsr(IA32_PLATFORM_ID);
+ int vid_max=msr.lo & 0x3f;
+
+ msr.lo &= ~0xffff;
+ msr.lo |= busratio_max << 8;
+ msr.lo |= vid_max;
+
+ wrmsr(IA32_PERF_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa