diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2008-10-29 04:48:44 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2008-10-29 04:48:44 +0000 |
commit | 00a889c8aabd7b731622d5ff0e765f69e158de2b (patch) | |
tree | fb10bfbf6a71bcc8ad583feb6b0c706abb86b6fa /src/cpu/intel/model_6ex/cache_as_ram_disable.c | |
parent | debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 (diff) |
Support for Intel Core Duo and Core 2 Duo (tm) CPUs.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/intel/model_6ex/cache_as_ram_disable.c')
-rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram_disable.c | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c new file mode 100644 index 0000000000..10e46656c1 --- /dev/null +++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "cpu/x86/car/copy_and_run.c" + +void real_main(unsigned long bist); + +void stage1_main(unsigned long bist) +{ + unsigned int cpu_reset = 0; + +#if USE_FALLBACK_IMAGE == 1 + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } else { + /* This is the primary cpu how should I boot? */ + check_cmos_failed(); + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + ); + fallback_image: +#endif + + real_main(bist); + + /* No servicable parts below this line .. */ + + { + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n\t" + : "=a" (v_esp) + ); + printk_spew("v_esp=%08x\r\n", v_esp); + } + +cpu_reset_x: + + printk_spew("cpu_reset = %08x\r\n",cpu_reset); + + if(cpu_reset == 0) { + print_spew("Clearing initial memory region: "); + } + print_spew("No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + + if(cpu_reset==0) { +#define CLEAR_FIRST_1M_RAM 1 +#include "cache_as_ram_post.c" + } else { +#undef CLEAR_FIRST_1M_RAM +#include "cache_as_ram_post.c" + } + + __asm__ volatile ( + /* set new esp */ /* before _RAMBASE */ + "subl %0, %%ebp\n\t" + "subl %0, %%esp\n\t" + ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n\t" + :"=a" (new_cpu_reset) + ); + + /* Copy and execute coreboot_ram */ + copy_and_run(new_cpu_reset); + /* We will not return */ + } + + print_debug("sorry. parachute did not open.\r\n"); +} |