diff options
author | Nico Huber <nico.huber@secunet.com> | 2019-02-27 14:29:24 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-28 13:48:37 +0000 |
commit | 1083a4d2324ce54f0a9f77098c8d7c23839c3849 (patch) | |
tree | 130a5e81f6271b42e3b2d12a3171979adcc736f1 /src/cpu/intel/model_6dx | |
parent | ec6d07a3309cf55b806b4306efbddc811648ae90 (diff) |
cpu/intel: Remove models 69x and 6dx
These came for the Socket 479 which is not supported anymore.
Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31644
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_6dx')
-rw-r--r-- | src/cpu/intel/model_6dx/Kconfig | 8 | ||||
-rw-r--r-- | src/cpu/intel/model_6dx/Makefile.inc | 3 | ||||
-rw-r--r-- | src/cpu/intel/model_6dx/model_6dx_init.c | 49 |
3 files changed, 0 insertions, 60 deletions
diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig deleted file mode 100644 index edbeac82de..0000000000 --- a/src/cpu/intel/model_6dx/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -config CPU_INTEL_MODEL_6DX - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc deleted file mode 100644 index 92985eab7c..0000000000 --- a/src/cpu/intel/model_6dx/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -ramstage-y += model_6dx_init.c - -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6dx/microcode.bin diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c deleted file mode 100644 index 337b6131df..0000000000 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> - -static void model_6dx_init(struct device *dev) -{ - /* Turn on caching if we haven't already */ - x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_6dx_init, -}; - -static const struct cpu_device_id cpu_table[] = { - /* Pentium M on 90nm with 2MiB of L2 cache */ - { X86_VENDOR_INTEL, 0x06D0 }, - { X86_VENDOR_INTEL, 0x06D6 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; |