move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.

this patch also slightly changes it so we have a single cache_as_ram.inc which
requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or
worse, a lot of cruft hacked right into romstage.c like on tyan s2735)

Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new
simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 0 insertions, 89 deletions

diff --git a/src/cpu/intel/model_6bx/cache_as_ram_disable.c b/src/cpu/intel/model_6bx/cache_as_ram_disable.c
deleted file mode 100644
index d3f34982b6..0000000000
--- a/src/cpu/intel/model_6bx/cache_as_ram_disable.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * This file is part of the coreboot project.
- * 
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/stages.h>
-
-/* called from assembler code */
-void stage1_main(unsigned long bist);
-
-/* from romstage.c */
-void real_main(unsigned long bist);
-
-void stage1_main(unsigned long bist)
-{
-	unsigned int cpu_reset = 0;
-
-	real_main(bist);
-
-	/* No servicable parts below this line .. */
-#ifdef CAR_DEBUG
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-	unsigned v_esp;
-	__asm__ volatile (
-        	"movl   %%esp, %0\n"
-		: "=a" (v_esp)
-	);
-	printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
-#endif
-
-        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
-	printk(BIOS_SPEW, "No cache as ram now - ");
-
-	/* store cpu_reset to ebx */
-        __asm__ volatile (
-                "movl %0, %%ebx\n\t"
-                ::"a" (cpu_reset)
-        );
-
-#undef CLEAR_FIRST_1M_RAM 
-#include "cpu/x86/car/cache_as_ram_post.c"
-
-	/* For now: use rambase + 1MB - 64K (counting downwards) as stack. This
-	 * makes sure that we stay completely within the 1M of memory we
-	 * preserve with the memcpy above.
-	 */
-
-#ifndef HIGH_MEMORY_SAVE
-#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
-#endif
-
-	__asm__ volatile (
-		"movl %0, %%ebp\n"
-		"movl %0, %%esp\n"
-		:: "a" (CONFIG_RAMBASE + HIGH_MEMORY_SAVE)
-	);
-
-	{
-		unsigned new_cpu_reset;
-
-		/* get back cpu_reset from ebx */
-		__asm__ volatile (
-			"movl %%ebx, %0\n"
-			:"=a" (new_cpu_reset)
-		);
-
-		/* Copy and execute coreboot_ram */
-		copy_and_run(new_cpu_reset);
-	}
-
-	/* We will not return */
-	printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
-}