Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.

abuild-tested. Boot tested on P2B-LS.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 82 insertions, 0 deletions

diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
new file mode 100644
index 0000000000..76a840e46e
--- /dev/null
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2010 Keith Hui <buurin@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+
+static const uint32_t microcode_updates[] = {
+	/* Include microcode updates here. */
+	#include "microcode-293-MU267114.h"
+	#include "microcode-530-MU16730e.h"
+	#include "microcode-531-MU26732e.h"
+	#include "microcode-539-MU167210.h"
+	#include "microcode-540-MU267238.h"
+	/* Dummy terminator */
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+};
+
+static void model_67x_init(device_t cpu)
+{
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Setup MTRRs */
+	x86_setup_mtrrs(36);
+	x86_mtrr_check();
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_67x_init,
+};
+
+/*
+ * Intel Pentium III Processor Identification and Package Information
+ * http://www.intel.com/design/pentiumiii/qit/update.pdf
+ *
+ * Intel Pentium III Processor Specification Update
+ * http://download.intel.com/design/intarch/specupdt/24445358.pdf
+ */
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0671 },
+	{ X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */
+	{ X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */
+
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};