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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2018-10-25 15:48:54 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:18:21 +0000 |
| commit | 319f0370bfe99ce47ea8b883696ad89d19b7c4b9 (patch) | |
| tree | 9a8a994ca2f1fd220e91e4ec62b54d89730899ca /src/cpu/intel/model_65x | |
| parent | 1a86cda6dbacfbae285fa3d44b3f67bea95367e3 (diff) | |
src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI
Code is based on microcode update procedure from fam10-15h with necessary
microcode blob structure updates for fam16h.
Currently updating microcode in romstage seem to be impossible. AGESA is
overriding the microcode patch regardles of the current microcode revision
patched on CPU. Use ramstage CPU init procedures to update microcode easily.
Tested with microcode blob 07030106 released 2018-02-09 from
platomav/CPUMicrocodes GitHub repository on apu2 platform.
TEST=boot Linux kernel 4.14.50 on PC Engines apu2 and run dmesg to see
patch_level=0x07030106 on all cores
Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29272
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_65x')
0 files changed, 0 insertions, 0 deletions