diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-04 11:58:37 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-07 04:56:21 +0000 |
| commit | 00c95b13ab8166c858a237f27077f51ebfcec5b1 (patch) | |
| tree | f571d448c592cf574e7ddb3f2e1d65f8a4d12df3 /src/cpu/intel/model_206ax | |
| parent | 42b6309595bfcf8b3ab9926033e98d682322a8cb (diff) | |
cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
The MSR only needs to be set when IO MWAIT redirection is to be enabled.
Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/cpu/intel/model_206ax')
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index beb885ea72..7a40644a6f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -172,12 +172,6 @@ static void configure_c_states(void) msr.lo |= (1 << 15); // Lock C-State MSR wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); - msr.lo &= ~0x7ffff; - msr.lo |= (PMB0_BASE + 4); // LVL_2 base address - msr.lo |= (2 << 16); // CST Range: C7 is max C-state - wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); - msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination wrmsr(MSR_MISC_PWR_MGMT, msr); |