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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-15 17:16:59 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-16 04:13:06 +0100
commit7b5f12b9b2695359b6ccb4d62bdb868166c7f8d1 (patch)
tree6b04150aa316965fd472b3dc127c374df6b34469 /src/cpu/intel/model_206ax
parentdfc8a560d7fec715a652f428dc3cab3e0a92c680 (diff)
cpu/intel: Indent with tabs
Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/model_206ax')
-rw-r--r--src/cpu/intel/model_206ax/model_206ax.h4
-rw-r--r--src/cpu/intel/model_206ax/model_206ax_init.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 5fb5c8f9f3..594dde143c 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -30,7 +30,7 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_PERF_CTL 0x199
+#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -38,7 +38,7 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
+#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index af712d0db5..ff4fad5e12 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -336,7 +336,7 @@ static void configure_misc(void)
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
- msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);