diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2012-06-19 12:56:57 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-07-24 22:15:19 +0200 |
| commit | 537b4e09e644107ed644cd88f8a7fd488406b9a2 (patch) | |
| tree | 92b1fc622e2f89c55149064396459ac362f2be17 /src/cpu/intel/model_206ax/model_206ax_init.c | |
| parent | ef6b08cc486e5d97103211dfeb3d629552a92e43 (diff) | |
Add code to read Intel microcode from CBFS
When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in
CBFS and pass it to intel_update_microcode() instead of using the
compiled in array.
CBFS accesses in pre-RAM and 'normal' environments are provided
through different API.
Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/1296
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/intel/model_206ax/model_206ax_init.c')
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index dda7d354b7..87bc585d86 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -115,9 +115,11 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; +#if !CONFIG_MICROCODE_IN_CBFS static const uint32_t microcode_updates[] = { #include "microcode_blob.h" }; +#endif /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -387,8 +389,11 @@ static void model_206ax_init(device_t cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Update the microcode */ +#if CONFIG_MICROCODE_IN_CBFS + intel_update_microcode_from_cbfs(); +#else intel_update_microcode(microcode_updates); +#endif /* Clear out pending MCEs */ configure_mca(); |