diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2012-10-25 09:37:19 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 03:27:45 +0100 |
| commit | 5986edadff53075f4bb5fe419514962c96f9faf6 (patch) | |
| tree | ab76a8d87ed2c6b3d5c769a7e5a4faa0ac350086 /src/cpu/intel/model_206ax/finalize.c | |
| parent | bb9dff55560e2f1834ec9bb41d4929ed3c749818 (diff) | |
Revert "Remove code that enables/disables VMX in coreboot on chromebooks."
The MSR for VMX can start with a random value and needs to be
cleared by coreboot. I am reverting this change, as
it handles almost everything and doing a follow-on change to fix
the improper clearing of the MSR.
Change-Id: Ibad7a27b03f199241c52c1ebdd2b6d4e81a18a4e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1793
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_206ax/finalize.c')
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 4ed5d1e5f8..ca7048d50b 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -43,6 +43,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { + msr_set_bit(IA32_FEATURE_CONTROL, 0); msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ |