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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 12:16:24 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:53:48 +0000 |
| commit | 6fcd7b8eb1ee650daa939593e8cbb3939f7c1188 (patch) | |
| tree | 0abd85cd08ef06b2d089711a2a3463a454d8ea7f /src/cpu/intel/model_206ax/Makefile.inc | |
| parent | c2ccc9782d1151efb7eba3ea92feded2ed555391 (diff) | |
cpu/intel/model_206ax: Switch to POSTCAR_STAGE
Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin.
Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/model_206ax/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/model_206ax/Makefile.inc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 0e2733e279..f6084ee202 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -12,16 +12,13 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc -else cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S -endif romstage-y += ../car/romstage.c |