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authorMartin Roth <martin.roth@se-eng.com>2013-07-08 16:23:54 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-11 22:36:59 +0200
commit4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c (patch)
tree6bd8440a05f6ea1184c0a5500d43cc92ab683f01 /src/cpu/intel/model_2065x
parent0cb07e3476d9408d0935253f9f26c0a8ddc28401 (diff)
cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_2065x')
-rw-r--r--src/cpu/intel/model_2065x/model_2065x_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index ab4db59e6d..4c88e4412f 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -39,7 +39,7 @@
#include "chip.h"
/*
- * List of suported C-states in this processor
+ * List of supported C-states in this processor
*
* Latencies are typical worst-case package exit time in uS
* taken from the SandyBridge BIOS specification.
@@ -249,7 +249,7 @@ static void configure_thermal_target(void)
return;
conf = lapic->chip_info;
- /* Set TCC activaiton offset if supported */
+ /* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);