diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-08 12:13:15 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-11 18:52:09 +0100 |
| commit | 39915bc290066174b8b933829b7d192b86bb8e6f (patch) | |
| tree | fb283a5f20bfa68e470532f4823640278662de1f /src/cpu/intel/model_2065x | |
| parent | a4ffe9dda0eb50eb698fef303f426408338fa0ff (diff) | |
intel cache-as-ram: Unify stack setup
No need to have %ebx reserved here.
Change-Id: I9fe9292ddc610079b876019a71c69af5b1bcf2a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17357
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/model_2065x')
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 29ff01a26a..93d690748f 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -156,8 +156,8 @@ clear_var_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Set up the stack pointer below the end of CAR. */ - movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp /* Restore the BIST result. */ @@ -169,11 +169,10 @@ before_romstage: post_code(0x29) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use * after cache-as-ram is torn down. */ - movl %eax, %ebx + movl %eax, %esp post_code(0x30) @@ -272,11 +271,7 @@ before_romstage: __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - - /* Setup stack as indicated by return value from romstage_main(). */ - movl %ebx, %esp - movl %esp, %ebp - call copy_and_run + call romstage_after_car .Lhlt: post_code(POST_DEAD_CODE) |