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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-18 14:51:41 -0600 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-06 04:09:47 +0000 |
| commit | 47818b4d6017b89e398cfbc86e3c437e0f81cfdf (patch) | |
| tree | e48d6742987cb1bea9c0a86edd2f8170ad4acb6a /src/cpu/intel/model_2065x | |
| parent | cc3284219460351c00a153b204a561a89bcec92e (diff) | |
fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
mess of it, by forcing a build-time error when CONFIG_POST_IO was not
being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
"select POST_IO" from boards that have it. Instead of implementing an
ad-hoc changing post code display and a delay based on port 0xed, just
encode the FSP failure code in the POST code. Since FSP failure codes
are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble.
Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8485
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/cpu/intel/model_2065x')
0 files changed, 0 insertions, 0 deletions