diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-13 00:54:32 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-14 02:24:39 +0000 |
| commit | 1b46e76df9ef0a4b38d782732ee914ab70667bfa (patch) | |
| tree | 83b3471f79037cc7376e2817ddd2905922d4f7eb /src/cpu/intel/model_2065x | |
| parent | e3f7ef22864402e72e1fa6c1df3bc79199c40bdc (diff) | |
include/cpu/x86/msr: introduce IA32_MC_*(x) macros
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4
and added to the IA32_MC0_* define to get the MSR number. Add a macro
that already does this calculation to avoid open coding this repeatedly.
Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_2065x')
| -rw-r--r-- | src/cpu/intel/model_2065x/model_2065x_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index dd2aeef135..abf8f610b9 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -81,7 +81,7 @@ static void configure_mca(void) msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ for (i = 0; i < 7; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); } static void model_2065x_init(struct device *cpu) |