diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-05-15 16:45:21 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-27 17:25:57 +0000 |
commit | 97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f (patch) | |
tree | 30a67e32ce77415b5b4f8734029a2037e4a7a6d5 /src/cpu/intel/model_2065x/model_2065x.h | |
parent | b66ee5507c4c2395868a5cd350dc8a7eb46542fd (diff) |
cpu/intel/model_2065x: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/cpu/intel/model_2065x/model_2065x.h')
-rw-r--r-- | src/cpu/intel/model_2065x/model_2065x.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 904e794219..e7ba2a771b 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -80,4 +80,22 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif +/* + * Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. + */ +#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE +#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE) + +/* Sanity check config options. */ +#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE) +# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE" +#endif +#if (CONFIG_SMM_TSEG_SIZE < 0x800000) +# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" +#endif +#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) +# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" +#endif + #endif |