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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-05 18:05:17 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-24 22:56:52 +0000 |
| commit | e39becf5216419fa0a08c1d8632474fd8a9a5738 (patch) | |
| tree | e4baed9dcf299738c09930d12421672b0133c478 /src/cpu/intel/model_106cx | |
| parent | c00e2fb9966a9c4bd30944a198ad036ee81a2b0d (diff) | |
intel/cpu: Switch older models to TSC_MONOTONIC_TIMER
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.
Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_106cx')
| -rw-r--r-- | src/cpu/intel/model_106cx/Kconfig | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index ba8557c3de..43c4048786 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -6,7 +6,9 @@ config CPU_INTEL_MODEL_106CX select ARCH_RAMSTAGE_X86_32 select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE |