diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-05-02 16:41:55 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-03 19:49:21 +0200 |
| commit | 3b5a9edcb2153d9a9530dcd50b5eb2f844faef5d (patch) | |
| tree | 3d64fccec30051c9d1df18cb75c549a734dcaa36 /src/cpu/intel/microcode | |
| parent | 8bec7fbc0f59926a487dcbeeb78402016752bdfc (diff) | |
Fix register corruption during Intel Microcode update
Another bug in the Intel microcode update code that existed since we switched
to LinuxBIOSv2 in 2004:
The inline assembly code that reads the CPU revision from an MSR after running
cpuid(1) trashes registers EBX and ECX. Only ECX was mentioned in the clobber
list. C code running after this function could silently access completely wrong
data, which resulted in the wrong date being printed on microcode updates (and
potentially other issues happening until the C code writes to EBX again)
Change-Id: Ida733fa1747565ec9824d3a37d08b1a73cd8355f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/996
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/intel/microcode')
| -rw-r--r-- | src/cpu/intel/microcode/microcode.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index ae1c26a4b5..ec42fb91d7 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -63,7 +63,7 @@ static inline u32 read_microcode_rev(void) "=a" (msr.lo), "=d" (msr.hi) : /* inputs */ : /* trashed */ - "ecx" + "ebx", "ecx" ); return msr.hi; } |