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| author | Wim Vervoorn <wvervoorn@eltan.com> | 2019-12-13 14:28:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-17 13:17:08 +0000 |
| commit | 555efe47922c8b347ad7cd2c9759740e3e228164 (patch) | |
| tree | 63fd7372350dcfb89f8bc24cfac2f7e3e49df832 /src/cpu/intel/haswell | |
| parent | f4b9ec67842fa169134d87e3e236c1f8525b8cdc (diff) | |
soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB
Skylake soc code sets the length of the PCIe configuration space to 64
MB while the specification allows up to 256 MB. Linux reports "acpi
PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bos 00-3f] only
partially covers this bridge".
Remove "select PCIEX_LENGTH_64MB" from Kconfig so the default 256MB will
be used and the size can be reduced on the mainboard level when required.
BUG=N/A
TEST=tested on facebook monolith
Tested is by booting Linux 4.15 and analyzing the coreboot and Linux
dmesg to make sure the memory range is reported correctly and doesn't
create an overlap.
Change-Id: I8a06b9fba5ad561d8595292a73136091ab532faa
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell')
0 files changed, 0 insertions, 0 deletions