diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-24 13:43:40 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-28 17:48:42 +0000 |
| commit | ffdee287df7a294396f1c935e1171dad7c44dbf3 (patch) | |
| tree | 2a213a933512f1cfe75ef01e954facb90bdf7656 /src/cpu/intel/haswell | |
| parent | 5f46af6325b5facb9a608b0f86595b92b98ed718 (diff) | |
cpu/intel: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/bootblock.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 0522f94c9a..57e1bbb30f 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -24,7 +24,7 @@ #include <cpu/intel/microcode/microcode.c> #include "haswell.h" -#if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/lynxpoint/pch.h> #else diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ac45ee62ad..c6162dcc84 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -34,7 +34,7 @@ #include <romstage_handoff.h> #include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include "haswell.h" @@ -182,7 +182,7 @@ void romstage_common(const struct romstage_params *params) wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif @@ -197,7 +197,7 @@ void romstage_common(const struct romstage_params *params) printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); if (wake_from_s3) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); @@ -239,7 +239,7 @@ void romstage_common(const struct romstage_params *params) /* Save data returned from MRC on non-S3 resumes. */ save_mrc_data(params->pei_data); } else if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ reset_system(); #endif |