diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 18:08:50 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 04:14:09 +0100 |
| commit | 26eeb0f8ad554b1fa08d58080da8ce2d22081c1c (patch) | |
| tree | 2b960b57e2175c94a852ca52e1c0db4abd1a69fb /src/cpu/intel/haswell | |
| parent | 73a28942031675fce20d6649d2c2ce66fe62f416 (diff) | |
cpu/intel: Fix brace issues detected by checkpatch.pl
Fix the following error and warning detected by checkpatch.pl:
ERROR: that open brace { should be on the previous line
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: Icdd6bd9ae578589b4d42002d200fa8f83920265e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18849
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/smmrelocate.c | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 89869e4418..0f6be3988f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -792,9 +792,8 @@ static const struct mp_ops mp_ops = { void bsp_init_and_start_aps(struct bus *cpu_bus) { - if (mp_init_with_smm(cpu_bus, &mp_ops)) { + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); - } } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index a1a6c317fa..c6765c757c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -248,9 +248,8 @@ void romstage_common(const struct romstage_params *params) romstage_handoff_init(wake_from_s3); post_code(0x3f); - if (IS_ENABLED(CONFIG_LPC_TPM)) { + if (IS_ENABLED(CONFIG_LPC_TPM)) init_tpm(wake_from_s3); - } } asmlinkage void romstage_after_car(void) diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3ec009ec37..e7a9ee1620 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -330,9 +330,8 @@ void smm_initialize(void) */ smm_initiate_relocation(); - if (smm_reloc_params.smm_save_state_in_msrs) { + if (smm_reloc_params.smm_save_state_in_msrs) printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n"); - } } /* The default SMM entry can happen in parallel or serially. If the |