diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-26 13:25:30 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:55:44 +0000 |
commit | a6a396ddb6f866c5a675dff5c1aa0b4cbaf44039 (patch) | |
tree | 64f29e2f33a26eff273488f68fc12cf9b5cc086b /src/cpu/intel/haswell | |
parent | 3286848a7a013b4d4effc4e50b4b7b552236cf73 (diff) |
cpu/intel/{haswell,model_206{5,a}x}: Use MSR_CORE_THREAD_COUNT for msr at 0x35
Regarding 64 and IA-32 Architectures Software Developer’s Manual, the register
name of the msr at 0x35 is MSR_CORE_THREAD_COUNT.
Change-Id: I5134619dc3a42187ddd5f46c85873c4278229e27
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33015
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell')
-rw-r--r-- | src/cpu/intel/haswell/haswell.h | 2 | ||||
-rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 3dfdd8d071..4ebbe183b7 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -34,7 +34,7 @@ /* Haswell bus clock is fixed at 100MHz */ #define HASWELL_BCLK 100 -#define CORE_THREAD_COUNT_MSR 0x35 +#define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 25cf243aca..95d719c2f1 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -732,7 +732,7 @@ static int get_cpu_count(void) int num_threads; int num_cores; - msr = rdmsr(CORE_THREAD_COUNT_MSR); + msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |