haswell: Misc power management setup and fixes

1) fix enable of power aware interrupt routing
2) set BIOS_RESET_CPL to 3 instead of 1
3) mirror PKG power limit values from MSR to MMIO on all SKUs
4) mirror DDR power limit values from MMIO to MSR
5) remove DMI settings that were from snb/ivb as they do
not apply to haswell

1) verify power aware interrupt routing is working by looking
in /proc/interrupts to see interrupts routed to both cores
instead of always to core0

BEFORE: 58:       4943          0   PCI-MSI-edge      ahci
AFTER:  58:       4766        334   PCI-MSI-edge      ahci

2) read back BIOS_RESET_CPL to verify it is == 3

localhost ~ # iotools mmio_read32 0xfed15da8
0x00000003

3) read PKG power limit from MMIO and verify it is the same
as the MSR value

localhost ~ # rdmsr 0 0x610
0x0000809600dc8078
localhost ~ # iotools mmio_read32 0xfed159a0
0x00dc8078
localhost ~ # iotools mmio_read32 0xfed159a4
0x00008096

4) read DDR power limit from MSR and verify it is the same
as the MMIO value (note this is zero based on current MRC input)

localhost ~ # rdmsr 0 0x618
0x0000000000000000
localhost ~ # iotools mmio_read32 0xfed158e0
0x00000000
localhost ~ # iotools mmio_read32 0xfed158e4
0x00000000

Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60544
Reviewed-on: http://review.coreboot.org/4333
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)

2 files changed, 12 insertions, 2 deletions

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index cd007c1f7e..387521722a 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -85,6 +85,7 @@
 #define MSR_VR_CURRENT_CONFIG		0x601
 #define MSR_PKG_POWER_SKU_UNIT		0x606
 #define MSR_PKG_POWER_SKU		0x614
+#define MSR_DDR_RAPL_LIMIT		0x618
 #define MSR_PP0_POWER_LIMIT		0x638
 #define MSR_PP1_POWER_LIMIT		0x640
 
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index b2e6eaf324..fb78df419a 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -361,7 +361,7 @@ void set_power_limits(u8 power_limit_1_time)
 	u8 power_limit_1_val;
 
 	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
-		return;
+		power_limit_1_time = 28;
 
 	if (!(msr.lo & PLATFORM_INFO_SET_TDP))
 		return;
@@ -401,10 +401,19 @@ void set_power_limits(u8 power_limit_1_time)
 	limit.hi = 0;
 	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
 	limit.hi |= PKG_POWER_LIMIT_EN;
-	/* Power limit 2 time is only programmable on SNB EP/EX */
+	/* Power limit 2 time is only programmable on server SKU */
 
 	wrmsr(MSR_PKG_POWER_LIMIT, limit);
 
+	/* Set power limit values in MCHBAR as well */
+	MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo;
+	MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
+
+	/* Set DDR RAPL power limit by copying from MMIO to MSR */
+	msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
+	msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
+	wrmsr(MSR_DDR_RAPL_LIMIT, msr);
+
 	/* Use nominal TDP values for CPUs with configurable TDP */
 	if (cpu_config_tdp_levels()) {
 		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);