diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-07-09 15:34:25 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-12-12 22:05:57 +0100 |
| commit | 118d105a375618a8ee8309cd9dcdc17ea6d31f30 (patch) | |
| tree | 4bbfc89771bcf71eb090bf9ae3a90be1091509a2 /src/cpu/intel/haswell | |
| parent | f6d6e62aaf76ba4bef5e0dcdfc73975c25f5337b (diff) | |
haswell: Export functions for CPU family+model and stepping
These are needed to enable workarounds/features on specific
CPU types and stepping. The older northbridge function and
defines from sandybridge/ivybridge are removed.
Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61333
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4355
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 19 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 22 |
2 files changed, 34 insertions, 7 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index e8c224944a..9ed00af632 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -24,8 +24,20 @@ #include <arch/cpu.h> +/* Haswell CPU types */ +#define HASWELL_FAMILY_MOBILE 0x306c0 +#define HASWELL_FAMILY_ULT 0x40650 + +/* Haswell CPU steppings */ +#define HASWELL_STEPPING_MOBILE_A0 1 +#define HASWELL_STEPPING_MOBILE_B0 2 +#define HASWELL_STEPPING_MOBILE_C0 3 +#define HASWELL_STEPPING_MOBILE_D0 4 +#define HASWELL_STEPPING_ULT_B0 0 +#define HASWELL_STEPPING_ULT_C0 1 + /* Haswell bus clock is fixed at 100MHz */ -#define HASWELL_BCLK 100 +#define HASWELL_BCLK 100 #define CORE_THREAD_COUNT_MSR 0x35 #define IA32_FEATURE_CONTROL 0x3a @@ -219,6 +231,11 @@ struct ramstage_cache { char program[0]; } __attribute__((packed)); +/* CPU identification */ +int haswell_family_model(void); +int haswell_stepping(void); +int haswell_is_ult(void); + #endif #endif diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index adc99cfd48..f8d295e066 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -207,13 +207,23 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; +int haswell_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +int haswell_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + /* Dynamically determine if the part is ULT. */ -static int is_ult(void) +int haswell_is_ult(void) { static int ult = -1; if (ult < 0) - ult = (cpuid_eax(1) > 0x40650); + ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); return ult; } @@ -308,7 +318,7 @@ static void initialize_vr_config(void) msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ - if (is_ult()) + if (haswell_is_ult()) msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ /* Leave the max instantaneous current limit (12:0) to default. */ wrmsr(MSR_VR_CURRENT_CONFIG, msr); @@ -334,7 +344,7 @@ static void initialize_vr_config(void) wrmsr(MSR_VR_MISC_CONFIG, msr); /* Configure VR_MISC_CONFIG2 MSR. */ - if (is_ult()) { + if (haswell_is_ult()) { msr = rdmsr(MSR_VR_MISC_CONFIG2); msr.lo &= ~0xffff; /* Allow CPU to control minimum voltage completely (15:8) and @@ -521,7 +531,7 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); /* Haswell ULT only supoprts the 3-5 latency response registers.*/ - if (is_ult()) { + if (haswell_is_ult()) { /* C-state Interrupt Response Latency Control 3 - package C8 */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_1024_NS | @@ -698,7 +708,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) initialize_vr_config(); - if (is_ult()) { + if (haswell_is_ult()) { calibrate_24mhz_bclk(); configure_pch_power_sharing(); } |