diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 17:40:50 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 04:13:24 +0100 |
| commit | 9d62e7e75e43d6737df9d0ab5603446d7f5e408d (patch) | |
| tree | 318963e23b89ca65cc05502774d0af1e831af578 /src/cpu/intel/haswell | |
| parent | 7b5f12b9b2695359b6ccb4d62bdb868166c7f8d1 (diff) | |
cpu/intel: Fix the spacing issues
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: need consistent spacing around '-' (ctx:WxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: need consistent spacing around '<<' (ctx:VxW)
ERROR: spaces required around that '||' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration
TEST=Build and run on Galileo Gen2
Change-Id: I6602fbc8602171ab6c2f3b6c204558ad2c811179
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/acpi.c | 4 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 4 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 4 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index d8962ee581..74d8fba55d 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -314,8 +314,8 @@ void generate_cpu_entries(device_t device) numcpus, cores_per_package); for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID=1; coreID<=cores_per_package; coreID++) { - if (coreID>1) { + for (coreID = 1; coreID <= cores_per_package; coreID++) { + if (coreID > 1) { pcontrol_blk = 0; plen = 0; } diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 2ab299a6d5..608c5b5908 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -180,10 +180,10 @@ void romstage_common(const struct romstage_params *params); * +32: MTRR mask 1 63:32 * ... */ -void * asmlinkage romstage_main(unsigned long bist); +asmlinkage void *romstage_main(unsigned long bist); /* romstage_after_car() is the C function called after cache-as-ram has * been torn down. It is responsible for loading the ramstage. */ -void asmlinkage romstage_after_car(void); +asmlinkage void romstage_after_car(void); #endif #ifdef __SMM__ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index d7ff121df4..ba6d83b785 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -87,12 +87,12 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { [C_STATE_C1] = { .latency = 0, .power = 1000, - .resource = MWAIT_RES(0,0), + .resource = MWAIT_RES(0, 0), }, [C_STATE_C1E] = { .latency = 0, .power = 1000, - .resource = MWAIT_RES(0,1), + .resource = MWAIT_RES(0, 1), }, [C_STATE_C3] = { .latency = C_STATE_LATENCY_FROM_LAT_REG(0), diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 351c05d87b..a1a6c317fa 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -140,7 +140,7 @@ static void *setup_romstage_stack_after_car(void) return slot; } -void * asmlinkage romstage_main(unsigned long bist) +asmlinkage void *romstage_main(unsigned long bist) { int i; void *romstage_stack_after_car; @@ -253,7 +253,7 @@ void romstage_common(const struct romstage_params *params) } } -void asmlinkage romstage_after_car(void) +asmlinkage void romstage_after_car(void) { /* Load the ramstage. */ run_ramstage(); |