cpu: Fix spelling

Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

4 files changed, 11 insertions, 11 deletions

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 4a739a9e30..ac082b86eb 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -169,7 +169,7 @@ void smm_initiate_relocation(void);
 void smm_initiate_relocation_parallel(void);
 struct bus;
 void bsp_init_and_start_aps(struct bus *cpu_bus);
-/* Returns 0 on succes. < 0 on failure. */
+/* Returns 0 on success. < 0 on failure. */
 int setup_ap_init(struct bus *cpu_bus, int *max_cpus,
                   const void *microcode_patch);
 /* Returns 0 on success, < 0 on failure. */
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 056b289bb2..85f6afd031 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -39,7 +39,7 @@
 #include "chip.h"
 
 /*
- * List of suported C-states in this processor
+ * List of supported C-states in this processor
  *
  * Latencies are typical worst-case package exit time in uS
  * taken from the SandyBridge BIOS specification.
@@ -324,7 +324,7 @@ static void configure_thermal_target(void)
 		return;
 	conf = lapic->chip_info;
 
-	/* Set TCC activaiton offset if supported */
+	/* Set TCC activation offset if supported */
 	msr = rdmsr(MSR_PLATFORM_INFO);
 	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
 		msr = rdmsr(MSR_TEMPERATURE_TARGET);
@@ -508,8 +508,8 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
 	int num_aps;
 	const void *microcode_patch;
 
-	/* Perform any necesarry BSP initialization before APs are brought up.
-	 * This call alos allows the BSP to prepare for any secondary effects
+	/* Perform any necessary BSP initialization before APs are brought up.
+	 * This call also allows the BSP to prepare for any secondary effects
 	 * from calling cpu_initialize() such as smm_init(). */
 	bsp_init_before_ap_bringup(cpu_bus);
 
@@ -529,7 +529,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
 	}
 
 	if (smm_initialize()) {
-		printk(BIOS_CRIT, "SMM Initialiazation failed...\n");
+		printk(BIOS_CRIT, "SMM Initialization failed...\n");
 		return;
 	}
 
diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c
index 1358418557..51130a56a3 100644
--- a/src/cpu/intel/haswell/mp_init.c
+++ b/src/cpu/intel/haswell/mp_init.c
@@ -78,7 +78,7 @@ static device_t cpu_devs[CONFIG_MAX_CPUS];
 static atomic_t num_aps;
 /* Number of APs that have relocated their SMM handler. */
 static atomic_t num_aps_relocated_smm;
-/* Barrier to stop APs from performing SMM relcoation. */
+/* Barrier to stop APs from performing SMM relocation. */
 static int smm_relocation_barrier_begin __attribute__ ((aligned (64)));
 /* Determine if hyperthreading is disabled. */
 int ht_disabled;
@@ -145,7 +145,7 @@ void release_aps_for_smm_relocation(int do_parallel)
 
 /* The mtrr code sets up ROM caching on the BSP, but not the others. However,
  * the boot loader payload disables this. In order for Linux not to complain
- * ensure the caching is disabled for tha APs before going to sleep. */
+ * ensure the caching is disabled for the APs before going to sleep. */
 static void cleanup_rom_caching(void)
 {
 	x86_mtrr_disable_rom_caching();
@@ -178,7 +178,7 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr)
 
 	ap_initiate_smm_relocation();
 
-	/* Indicate that SMM relocation has occured on this thread. */
+	/* Indicate that SMM relocation has occurred on this thread. */
 	atomic_inc(&num_aps_relocated_smm);
 
 	/* After SMM relocation a 2nd microcode load is required. */
@@ -401,7 +401,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads)
 		/* Allocate the new cpu device structure */
 		new = alloc_find_dev(cpu_bus, &cpu_path);
 		if (new == NULL) {
-			printk(BIOS_CRIT, "Could not allocte cpu device\n");
+			printk(BIOS_CRIT, "Could not allocate cpu device\n");
 			max_cpus--;
 		}
 		cpu_devs[i] = new;
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 4fe6489be2..3f4f45ab4f 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -348,7 +348,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 	memset(ied_base + (1 << 20), 0, (32 << 10));
 
 	/* According to the BWG MP init section 2MiB of memory at IEDBASE +
-	 * 2MiB should be zeroed as well. However, I suspect what is inteneded
+	 * 2MiB should be zeroed as well. However, I suspect what is intended
 	 * is to clear the memory covered by EMRR. TODO(adurbin): figure out if 	 * this is really required. */
 	//memset(ied_base + (2 << 20), 0, (2 << 20));
 }