diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/cpu/intel/haswell | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/bootblock.c | 2 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 3a306b5729..722cc0102e 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -23,7 +23,7 @@ #include <cpu/intel/microcode/microcode.c> #include "haswell.h" -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) +#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) /* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/lynxpoint/pch.h> #else diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index d5028c299b..1e5f3d3656 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -30,7 +30,7 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <vendorcode/google/chromeos/chromeos.h> -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> #endif #include <northbridge/intel/haswell/haswell.h> @@ -89,7 +89,7 @@ void romstage_common(const struct romstage_params *params) printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); if (wake_from_s3) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); @@ -131,7 +131,7 @@ void romstage_common(const struct romstage_params *params) /* Save data returned from MRC on non-S3 resumes. */ save_mrc_data(params->pei_data); } else if (cbmem_initialize()) { - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + #if CONFIG(HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ system_reset(); #endif |