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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-02 06:14:50 +0300 |
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committer | Martin Roth <martinroth@google.com> | 2019-08-03 17:33:41 +0000 |
commit | 825646e6431b51bd45349dbd2cb1d607e2eecae1 (patch) | |
tree | 642cf8f160a6108f9fa3844d203c4469819d118b /src/cpu/intel/haswell/stage_cache.c | |
parent | 641e0f68417bfff7fe11b854df04987a6c31c81b (diff) |
intel/haswell: Move stage_cache support function
Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.
Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE.
Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel/haswell/stage_cache.c')
-rw-r--r-- | src/cpu/intel/haswell/stage_cache.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c deleted file mode 100644 index 009cc09ba6..0000000000 --- a/src/cpu/intel/haswell/stage_cache.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include "haswell.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); -} |