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authorAaron Durbin <adurbin@chromium.org>2013-01-15 08:27:05 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-19 05:15:22 +0100
commit305b1f0d30b68c310d4dfa7e1a5f432769a65b31 (patch)
tree2f2846f6ca998bf27ac69d817b97c50ded36a845 /src/cpu/intel/haswell/smmrelocate.c
parent98ffb426f40593f930388c006f8058c199defff4 (diff)
haswell: Parallel AP bringup
This patch parallelizes the AP startup for Haswell-based devices. It does not touch the generic secondary startup code. Instead it provides its own MP support matching up with the Haswell BWG. It seemed to be too much trouble to support the old startup way and this new way. Because of that parallel loading is the only thing supported. A couple of things to note: 1. Micrcode needs to be loaded twice. Once before MTRR and caching is enabled. And a second time after SMM relocation. 2. The sipi_vector is entirely self-contained. Once it is loaded and written back to RAM the APs do not access memory outside of the sipi_vector load location until a sync up in ramstage. 3. SMM relocation is kicked off by an IPI to self w/ SMI set as the destination mode. The following are timings from cbmem with dev mode disabled and recovery mode enabled to boot directly into the kernel. This was done on the baskingridge CRB with a 4-core 8-thread CPU and 2 DIMMs 1GiB each. The kernel has console enabled on the serial port. Entry 70 is the device initialization, and that is where the APs are brought up. With these two examples it looks to shave off ~200 ms of boot time. Before: 1:55,382 2:57,606 (2,223) 3:3,108,983 (3,051,377) 4:3,110,084 (1,101) 8:3,113,109 (3,024) 9:3,156,694 (43,585) 10:3,156,815 (120) 30:3,157,110 (295) 40:3,158,180 (1,069) 50:3,160,157 (1,977) 60:3,160,366 (208) 70:4,221,044 (1,060,677) 75:4,221,062 (18) 80:4,227,185 (6,122) 90:4,227,669 (484) 99:4,265,596 (37,927) 1000:4,267,822 (2,225) 1001:4,268,507 (685) 1002:4,268,780 (272) 1003:4,398,676 (129,896) 1004:4,398,979 (303) 1100:7,477,601 (3,078,621) 1101:7,480,210 (2,608) After: 1:49,518 2:51,778 (2,259) 3:3,081,186 (3,029,407) 4:3,082,252 (1,066) 8:3,085,137 (2,884) 9:3,130,339 (45,202) 10:3,130,518 (178) 30:3,130,544 (26) 40:3,131,125 (580) 50:3,133,023 (1,897) 60:3,133,278 (255) 70:4,009,259 (875,980) 75:4,009,273 (13) 80:4,015,947 (6,674) 90:4,016,430 (482) 99:4,056,265 (39,835) 1000:4,058,492 (2,226) 1001:4,059,176 (684) 1002:4,059,450 (273) 1003:4,189,333 (129,883) 1004:4,189,770 (436) 1100:7,262,358 (3,072,588) 1101:7,263,926 (1,567) Booted the baskingridge board as noted above. Also analyzed serial messages with pcserial enabled. Change-Id: Ifedc7f787953647c228b11afdb725686e38c4098 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/smmrelocate.c')
-rw-r--r--src/cpu/intel/haswell/smmrelocate.c25
1 files changed, 16 insertions, 9 deletions
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 1ccc9bb5b3..4312d7953e 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
@@ -297,24 +298,30 @@ static int cpu_smm_setup(void)
return 0;
}
-void smm_init(void)
+int smm_initialize(void)
{
/* Return early if CPU SMM setup failed. */
if (cpu_smm_setup())
- return;
+ return -1;
southbridge_smm_init();
- /* Initiate first SMI to kick off SMM-context relocation. Note: this
- * SMI being triggered here queues up an SMI in the APs which are in
- * wait-for-SIPI state. Once an AP gets an SIPI it will service the SMI
- * at the SMM_DEFAULT_BASE before jumping to startup vector. */
- southbridge_trigger_smi();
-
- printk(BIOS_DEBUG, "Relocation complete.\n");
+ /* Run the relocation handler. */
+ smm_initiate_relocation();
/* Lock down the SMRAM space. */
smm_lock();
+
+ return 0;
+}
+
+void smm_init(void)
+{
+ /* smm_init() is normally called from initialize_cpus() in
+ * lapic_cpu_init.c. However, that path is no longer used. Don't reuse
+ * the function name because that would cause confusion.
+ * The smm_initialize() function above is used to setup SMM at the
+ * appropriate time. */
}
void smm_lock(void)