cpu/intel/haswell: Use the common intel romstage_main function

Tested on Google peppy (Acer C720).

Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 2 insertions, 29 deletions

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index ab9fd591be..0e91daee50 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -43,6 +43,7 @@
 #include "southbridge/intel/lynxpoint/pch.h"
 #include "southbridge/intel/lynxpoint/me.h"
 #include <security/tpm/tspi.h>
+#include <cpu/intel/romstage.h>
 
 static inline void reset_system(void)
 {
@@ -55,7 +56,7 @@ static inline void reset_system(void)
 /* platform_enter_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use,
  * and continues execution in postcar stage. */
-static void platform_enter_postcar(void)
+void platform_enter_postcar(void)
 {
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
@@ -80,34 +81,6 @@ static void platform_enter_postcar(void)
 	run_postcar_phase(&pcf);
 }
 
-asmlinkage void *romstage_main(unsigned long bist)
-{
-	int i;
-	const int num_guards = 4;
-	const u32 stack_guard = 0xdeadbeef;
-	u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
-				   CONFIG_DCACHE_RAM_SIZE -
-				   CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
-
-	printk(BIOS_DEBUG, "Setting up stack guards.\n");
-	for (i = 0; i < num_guards; i++)
-		stack_base[i] = stack_guard;
-
-	mainboard_romstage_entry(bist);
-
-	/* Check the stack. */
-	for (i = 0; i < num_guards; i++) {
-		if (stack_base[i] == stack_guard)
-			continue;
-		printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
-	}
-
-	platform_enter_postcar();
-
-	/* We do not return here */
-	return NULL;
-}
-
 void romstage_common(const struct romstage_params *params)
 {
 	int boot_mode;