diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-15 17:16:59 -0700 |
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committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-16 04:13:06 +0100 |
commit | 7b5f12b9b2695359b6ccb4d62bdb868166c7f8d1 (patch) | |
tree | 6b04150aa316965fd472b3dc127c374df6b34469 /src/cpu/intel/haswell/romstage.c | |
parent | dfc8a560d7fec715a652f428dc3cab3e0a92c680 (diff) |
cpu/intel: Indent with tabs
Fix the following error and warning detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/intel/haswell/romstage.c')
-rw-r--r-- | src/cpu/intel/haswell/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index c82f3b9831..351c05d87b 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -147,8 +147,8 @@ void * asmlinkage romstage_main(unsigned long bist) const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE - - CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); printk(BIOS_DEBUG, "Setting up stack guards.\n"); for (i = 0; i < num_guards; i++) |