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author | Shawn Nematbakhsh <shawnn@google.com> | 2013-05-08 11:41:04 -0700 |
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committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-01 23:19:38 +0100 |
commit | 932fbd659ac7bea41e977f5fb5315fcfc93d36dd (patch) | |
tree | b097680c82dc5eccebec5cc269cb3e14d4e304f2 /src/cpu/intel/haswell/romstage.c | |
parent | ce22cd066bfa1c3c2c24ef6c6759620c52aeba22 (diff) |
Add DDR refresh config to pei data structure.
Allow platform customized DDR config, including forcing refresh rate to
2x.
Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2
Reviewed-on: https://gerrit.chromium.org/gerrit/50476
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/romstage.c')
0 files changed, 0 insertions, 0 deletions