diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2013-03-07 14:08:04 -0800 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 23:06:56 +0100 |
commit | 1ad5564dd675a246f5b0a05d03482836d49d44a9 (patch) | |
tree | 8a014191ef33991fb0417ba58093f8d5702d243d /src/cpu/intel/haswell/haswell_init.c | |
parent | 5cc51c08cd44e2749f4a27775cefffd4b91e0a50 (diff) |
lynxpoint: Add helper functions for reading PM and GPIO base
These base addresses are used in several places and it
is helpful to have one location that is reading it.
Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2812
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/haswell_init.c')
-rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index c7f89ee646..0bb11a8ed0 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -267,7 +267,7 @@ static void configure_c_states(void) msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); msr.lo &= ~0x7ffff; - msr.lo |= (PMB0_BASE + 4); // LVL_2 base address + msr.lo |= (get_pmbase() + 4); // LVL_2 base address msr.lo |= (2 << 16); // CST Range: C7 is max C-state wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); |