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authorPaul Menzel <paulepanter@users.sourceforge.net>2014-01-25 15:55:28 +0100
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2014-01-26 15:59:46 +0100
commit4fe9813adb44b369c84a097b4be3101eddf6b19d (patch)
treed22eb1a875215c1e36666b85041483e291d028cc /src/cpu/intel/haswell/haswell.h
parentf927df68e491e3bb7bad02a405aae5fd91545155 (diff)
src/cpu: Fix spelling of MTTR to MTRR
Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4805 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
-rw-r--r--src/cpu/intel/haswell/haswell.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 9ed00af632..dcd5dc70ea 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -175,14 +175,14 @@ void romstage_common(const struct romstage_params *params);
* torn down. The following values are pushed onto the stack to setup the
* MTRRs:
* +0: Number of MTRRs
- * +4: MTTR base 0 31:0
- * +8: MTTR base 0 63:32
- * +12: MTTR mask 0 31:0
- * +16: MTTR mask 0 63:32
- * +20: MTTR base 1 31:0
- * +24: MTTR base 1 63:32
- * +28: MTTR mask 1 31:0
- * +32: MTTR mask 1 63:32
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
* ...
*/
void * asmlinkage romstage_main(unsigned long bist);