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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2024-09-20 22:25:58 +0300 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-10-07 21:08:10 +0000 |
| commit | 1ec25777df4bd40f174fd7083ce60aec46141e2b (patch) | |
| tree | 0e002578d5851faa58a1abf346e9250efa6a1f05 /src/cpu/intel/haswell/haswell.h | |
| parent | 8cf60670b22db5c66c8cdfded335b01321846e22 (diff) | |
soc/intel/cannonlake: Add missing USB port aliases
FSP for Comet Lake S allows one to configure 16 USB2 (PortUsb20Enable
array) ports and 10 USB3 (PortUsb30Enable array) ports [1, 2].
[1] src/soc/intel/cannonlake/chip.h
[2] 3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h
Change-Id: Ie69543f335be1a69cf0c068335c2e17eebf4c6a9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/haswell.h')
0 files changed, 0 insertions, 0 deletions