diff options
| author | Sol Boucher <solb@chromium.org> | 2015-04-30 18:02:08 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-05-05 03:39:41 +0200 |
| commit | 8ccdeaeb207031eea3881511acfaf3e949678f74 (patch) | |
| tree | 15ef6918fe8cb0f251cf7856a624e19e7be4d1fc /src/cpu/intel/haswell/Makefile.inc | |
| parent | 634899ca498fd91d4e0a742d5ff3c6c4864542d1 (diff) | |
haswell: Link stage_cache_external_region into ramstage, too
When CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is set, this
function is now linked into the ramstage as well as the romstage,
since the former makes calls to it in panther builds.
With this commit, it's possible to build panther using the config file
from the Chromium OS project[1] if you supply the appropriate Intel
descriptor and ME binary blobs and manually set
CONFIG_VBOOT_VERIFY_FIRMWARE=n, CONFIG_BUILD_WITH_FAKE_IFD=n, and
CONFIG_HAVE_ME_BIN=y. The resulting image is at least able to load a
payload, although I only tested with depthcharge, which immediately
complained, "vboot handoff pointer is NULL" and gave up the ghost.
[1] https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/master/sys-boot/coreboot/files/configs/config.panther
Change-Id: Id3bb510fa60129a4d36a0117dc33e7aa62d6c742
Signed-off-by: Sol Boucher <solb@chromium.org>
Reviewed-on: http://review.coreboot.org/10046
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/intel/haswell/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 0db047565c..57f9120d5a 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -4,9 +4,12 @@ romstage-y += romstage.c romstage-y += tsc_freq.c ramstage-y += acpi.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c |