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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 12:04:26 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:49:41 +0000 |
| commit | dd4d8951368029634f53e44e1a222417b72036c0 (patch) | |
| tree | 145e103037040f09438d5e41895ab0c6e51db4fe /src/cpu/intel/haswell/Makefile.inc | |
| parent | 3a4edb6ea815fa24f02daeae9b80e6bde0871a9e (diff) | |
cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support
Prepare a common cache as ram for CPU's featuring a Non eviction mode
MSR.
Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26789
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index bb0f376b92..dc7170b742 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -14,7 +14,12 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-y += monotonic_timer.c +ifneq ($(CONFIG_POSTCAR_STAGE),y) cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc +else +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +postcar-y += ../car/non-evict/exit_car.S +endif subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr |