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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 12:37:54 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:59:22 +0000 |
| commit | 88af0f38eb19f956e8df2b62254c10c7603a9a33 (patch) | |
| tree | 97fdbf21a0dca3c0f6c5473e9bf92c0b954df33a /src/cpu/intel/haswell/Makefile.inc | |
| parent | 02b13fd8cdfbfcb4858ec0e6f66688b96950198e (diff) | |
cpu/intel/haswell: Switch to POSTCAR_STAGE
Tested on Google Peppy (Acer C720).
Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26793
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/haswell/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index dc7170b742..a0c892a561 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -9,17 +9,14 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-y += monotonic_timer.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-y += monotonic_timer.c -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc -else cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S -endif subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr |