diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-04 19:34:59 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 10:01:35 +0000 |
| commit | faa5f9869d67ab1a963e1c49afaaf353503586c9 (patch) | |
| tree | a489e11b9225a4e93fefc42419095ce03f3eaee5 /src/cpu/intel/haswell/Makefile.inc | |
| parent | 5e2ac2c0795628ab086da76304cd97b16e1d169f (diff) | |
cpu/intel/haswell: Use the common intel romstage_main function
Tested on Google peppy (Acer C720).
Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/intel/haswell/Makefile.inc')
| -rw-r--r-- | src/cpu/intel/haswell/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index a0c892a561..bbd98da10b 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += haswell_init.c ramstage-y += tsc_freq.c romstage-y += romstage.c romstage-y += tsc_freq.c +romstage-y += ../car/romstage.c ramstage-y += acpi.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c |