aboutsummaryrefslogtreecommitdiff
path: root/src/cpu/intel/haswell/Makefile.inc
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-03 12:06:04 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-08 22:16:58 +0000
commit2e25ac6afe84d9535fa6d89b847915e96f5d266b (patch)
tree3c05edec71d4e1215d864eccb61a9ae0a0b7717e /src/cpu/intel/haswell/Makefile.inc
parent284a54775bf17f5192b164a4b9d09a06fcd747cd (diff)
haswell: relocate `romstage_common` to northbridge
Other platforms do this as well. It will ease refactoring on follow-ups. Change-Id: I643982a58c6f5370c78acef93740f27df001a06d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/cpu/intel/haswell/Makefile.inc')
-rw-r--r--src/cpu/intel/haswell/Makefile.inc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index aebeed497a..b93b911aeb 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -1,5 +1,4 @@
ramstage-y += haswell_init.c
-romstage-y += romstage.c
romstage-y += ../car/romstage.c
ramstage-y += acpi.c