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authorArthur Heymans <arthur@aheymans.xyz>2018-06-05 11:19:22 +0200
committerMartin Roth <martinroth@google.com>2019-04-21 23:31:26 +0000
commit8e646e74b3d5e1d4a5e8114f03046f3d7b6ad042 (patch)
tree1412f9f4cb0a07c145bc605b1087e96d4f62f8fc /src/cpu/intel/haswell/Kconfig
parentc4772b9fd7fcc29d09d7617dc8cff922118814d7 (diff)
cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by default. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/cpu/intel/haswell/Kconfig')
-rw-r--r--src/cpu/intel/haswell/Kconfig4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 3aadfdee5a..3fd8bb484a 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -24,10 +24,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP
select CPU_INTEL_COMMON
-config BOOTBLOCK_CPU_INIT
- string
- default "cpu/intel/haswell/bootblock.c"
-
config SMM_TSEG_SIZE
hex
default 0x800000