src/soc/intel/common/block/pcie/rtd3: Fix root port _STA logic

When enable_gpio is used as active low output, the _STA returns
incorrect value.

Also, simply the logic for _STA method.
When enable pin is used for _STA:
| polarity    | tx value| get_tx_gpio() | State |
| active high |    0    |     0         |   0   |
| active high |    1    |     1(active) |   1   |
| active low  |    0    |     1(active) |   1   |
| active low  |    1    |     0         |   0   |

When reset pin is used for _STA:
| polarity    | tx value| get_tx_gpio() | State |
| active high |    0    |     0         |   1   |
| active high |    1    |     1(active) |   0   |
| active low  |    0    |     1(active) |   0   |
| active low  |    1    |     0         |   1   |

Generated _STA method:

Ex: for using active low power enable GPIO pin GPPC_H17:
Method (_STA, 0, NotSerialized)  // _STA: Status
{
    Local0 = \_SB.PCI0.GTXS (0x5C)
    Local0 ^= One
    Return (Local0)
}

TEST=Check the SSDT when booted to OS.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie6f1e7a5b3e9fd0ea00e1e5b54058a14c6e9e09e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72421
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions