diff options
| author | Martin Roth <gaumless@gmail.com> | 2014-05-21 13:40:21 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-07-30 18:59:35 +0200 |
| commit | 09670265b63184f92d78fc8fe5311f3662cc528a (patch) | |
| tree | ffb44c4126b20845c4f202bb342c7f6d160bdf25 /src/cpu/intel/fsp_model_406dx/Kconfig | |
| parent | ddf54b1c8b2ef6e8e3d2a673e0dd1ab43c7edc2c (diff) | |
cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)
This adds the CPU initialization pieces for Intel's Atom C2000 processor
(Formerly Rangeley).
Change-Id: I77d69f42c959bbc294784f044b7b0dcc2e30f30c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/6368
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/cpu/intel/fsp_model_406dx/Kconfig')
| -rw-r--r-- | src/cpu/intel/fsp_model_406dx/Kconfig | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig new file mode 100644 index 0000000000..11a92a00fe --- /dev/null +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -0,0 +1,75 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_INTEL_FSP_MODEL_406DX + bool + +if CPU_INTEL_FSP_MODEL_406DX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select PLATFORM_USES_FSP + select ARCH_BOOTBLOCK_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select SMP + select SSE2 + select UDELAY_LAPIC + select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select PARALLEL_CPU_INIT + select TSC_SYNC_MFENCE + select LAPIC_MONOTONIC_TIMER + select BROKEN_CAR_MIGRATE + +choice + prompt "Rangeley CPU Stepping" + default FSP_MODEL_406DX_B0 + +config FSP_MODEL_406DX_A1 + bool "A1" + +config FSP_MODEL_406DX_B0 + bool "B0" + +endchoice + +config BOOTBLOCK_CPU_INIT + string + default "cpu/intel/fsp_model_406dx/bootblock.c" + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + +config CPU_MICROCODE_CBFS_LOC + hex + depends on SUPPORT_CPU_UCODE_IN_CBFS + default 0xfff60040 + +config CPU_MICROCODE_CBFS_LEN + hex + depends on SUPPORT_CPU_UCODE_IN_CBFS + default 0x14400 if FSP_MODEL_406DX_A1 + default 0x14800 if FSP_MODEL_406DX_B0 + +config MICROCODE_INCLUDE_PATH + string "Location of the intel microcode patches" + default "../intel/cpu/rangeley/microcode" + +endif #CPU_INTEL_FSP_MODEL_406DX |