diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-10-17 19:18:41 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-10-20 17:51:46 +0000 |
| commit | 6dff1fd7d5e419b2f947f516551dcab3f4ebe30a (patch) | |
| tree | 699f4cf1a0f2da74a8ec27f5619443fe986ce33c /src/cpu/intel/common | |
| parent | d947639a486beef26b8daa164e3e3832196903c9 (diff) | |
cpu/intel/common: Define build time physical address reserved bits
According the Intel Software Developer Manual,
CPUID.80000008H:EAX[15:8] reports the physical-address width supported
by the processor. Unfortunately, it does not necessarily reflect the
physical-address space the system can actulally use as some of those
bits can be reserved for internal hardware use.
It is critical for coreboot to know the actual physical address size.
Overestimating this size can lead to device resource overlaps due to
the hardware ignoring upper reserved bits. On rex for instance, it
creates some reboot hangs due to an overlap between thunderbolt and
Input Output Manager (IOM) address space.
As some SoCs, such as Meteor Lake, have physical address reserved bits
which cannot be probed at runtime, this commit introduces
`CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS' Kconfig to set the number
of physical address reserved bits at compilation time for those SoCs.
A runtime detection by hardware probing will be attempted if the value
is 0 (default).
BUG=b:288978352
Change-Id: I8748fa3e5bdfd339e973d562c5a201d5616f813e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78451
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/cpu/intel/common')
| -rw-r--r-- | src/cpu/intel/common/Kconfig | 8 | ||||
| -rw-r--r-- | src/cpu/intel/common/common_init.c | 3 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 51b8ccb83f..0f6bd6879a 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -31,6 +31,14 @@ config SET_MSR_AESNI_LOCK_BIT config CPU_INTEL_COMMON_TIMEBASE bool +config CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS + int + help + Specify the number of physical address reserved bits. This + config can be set for SoCs with reserved bits which cannot + be probed at runtime. A runtime detection by hardware + probing will be attempted if the value is -1. + endif config CPU_INTEL_COMMON_VOLTAGE diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 55bc59eb75..83a21e05ed 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -258,6 +258,9 @@ static unsigned int get_tme_keyid_bits(void) unsigned int get_reserved_phys_addr_bits(void) { + if (CONFIG_CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS) + return CONFIG_CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS; + if (!is_tme_supported()) return 0; |