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authorPaul Menzel <paulepanter@users.sourceforge.net>2015-10-13 21:07:32 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-10-23 22:28:12 +0200
commit469f593498cabf0bf205833bab4218e409929cf8 (patch)
tree751e8ec63228483317cf5072b4cd738979d72e3e /src/cpu/intel/common
parent6b0933adf71fc5ce234e9fd924839b6759d06d7c (diff)
cpu/intel: Move Power notification ASL code into `common/acpi`
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/cpu/intel/model_6dx/acpi`, although the devices can also use different Intel CPU models like, for example, `intel/model_6ex` on the Lenovo T60. Therefore move the file to the directory `src/cpu/intel/common/acpi` so that other devices, like Intel GM45 based devices, can also include it. Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/intel/common')
-rw-r--r--src/cpu/intel/common/acpi/cpu.asl37
1 files changed, 37 insertions, 0 deletions
diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl
new file mode 100644
index 0000000000..04438a227a
--- /dev/null
+++ b/src/cpu/intel/common/acpi/cpu.asl
@@ -0,0 +1,37 @@
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+// Power notification
+
+External (\_PR_.CP00, DeviceObj)
+External (\_PR_.CP01, DeviceObj)
+External (\_PR_.CP00._PPC)
+External (\_PR_.CP01._PPC)
+
+Method (PNOT)
+{
+ If (MPEN) {
+ If(And(PDC0, 0x08)) {
+ Notify (\_PR_.CP00, 0x80) // _PPC
+
+ If (And(PDC0, 0x10)) {
+ Sleep(100)
+ Notify(\_PR_.CP00, 0x81) // _CST
+ }
+ }
+
+ If(And(PDC1, 0x08)) {
+ Notify (\_PR_.CP01, 0x80) // _PPC
+ If (And(PDC1, 0x10)) {
+ Sleep(100)
+ Notify(\_PR_.CP01, 0x81) // _CST
+ }
+ }
+
+ } Else { // UP
+ Notify (\_PR_.CP00, 0x80)
+ Sleep(0x64)
+ Notify(\_PR_.CP00, 0x81)
+ }
+}