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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-11 14:05:32 +0200
committerNico Huber <nico.h@gmx.de>2020-10-24 09:46:45 +0000
commit10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 (patch)
treee71fa6148adb9895fbc02111a74a35b395a0794e /src/cpu/intel/common
parent29a52c8308ab270c46c1d859db308ba1de5d1e81 (diff)
{cpu,soc}/intel: deduplicate cpu code
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. This change just moves the code. Rework is done in CB:46588. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/common')
-rw-r--r--src/cpu/intel/common/common.h6
-rw-r--r--src/cpu/intel/common/common_init.c43
2 files changed, 49 insertions, 0 deletions
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index 57a51e5538..dd8c2b8a27 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -33,4 +33,10 @@ bool intel_ht_sibling(void);
*/
void set_aesni_lock(void);
+void enable_lapic_tpr(void);
+
+void configure_dca_cap(void);
+
+void set_energy_perf_bias(u8 policy);
+
#endif
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index a54e89183f..f4bf245c2f 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -4,6 +4,7 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/msr.h>
+#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include "common.h"
@@ -286,3 +287,45 @@ void set_aesni_lock(void)
msr_set(MSR_FEATURE_CONFIG, AESNI_LOCK);
}
+
+void enable_lapic_tpr(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(MSR_PIC_MSG_CONTROL);
+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
+ wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+void configure_dca_cap(void)
+{
+ uint32_t feature_flag;
+ msr_t msr;
+
+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+ feature_flag = cpu_get_feature_flags_ecx();
+ if (feature_flag & CPUID_DCA) {
+ msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+ msr.lo |= 1;
+ wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+ }
+}
+
+void set_energy_perf_bias(u8 policy)
+{
+ msr_t msr;
+ int ecx;
+
+ /* Determine if energy efficient policy is supported. */
+ ecx = cpuid_ecx(0x6);
+ if (!(ecx & (1 << 3)))
+ return;
+
+ /* Energy Policy is bits 3:0 */
+ msr = rdmsr(IA32_ENERGY_PERF_BIAS);
+ msr.lo &= ~0xf;
+ msr.lo |= policy & 0xf;
+ wrmsr(IA32_ENERGY_PERF_BIAS, msr);
+
+ printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);
+}